The need to reduce on-chip power consumption has continued to increase as the number of transistors within chips (e.g. microprocessors, graphics chips) increases and as electronic devices that use these chips are scaled down, for example, for greater mobility. Historically, the low power consumption targets of chips have been achieved by aggressively scaling down their power supply voltages.
In an effort to further reduce overall power consumption, many chip designs also include two or more different power supply domains. Non-critical blocks within a chip, for example, can be designed to consume minimal amounts of energy by tying them to lower power supply voltages in a low power supply domain. Within the same chip, timing critical blocks that require the stability associated with a high power domain can be designed to use higher power supply voltages. Often, voltage level shifters are used to convert voltages in the high power supply domain to voltages in the low power supply domain, and visa versa.
FIG. 1 shows a level shifter 100 in the form of a buffer, in accordance with the prior art. As shown, an input signal is received from a high voltage domain (e.g. VDDH domain) and an output signal is directed to a low voltage domain (e.g. VDDL domain). When the input signal is 0 (see state 102), transistors P1 and N2 are activated, and transistors N1 and P2 are deactivated. On the other hand, when the input signal is VDDH (see state 104), the transistors N1 and P2 are activated and the transistors P1 and N2 are deactivated. To this end, the illustrated buffer is capable of serving as a level shifter for converting a signal from the VDDH domain to the VDDL domain.
FIG. 2 shows a level shifter 200 in the form of a buffer that is adapted for converting an input signal from a VDDL domain to a VDDH domain, in accordance with the prior art. Similar to the level shifter 100 of FIG. 1, when the input signal is 0 (see state 202), transistors P1 and N2 are activated, and transistors N1 and P2 are deactivated. Further, when the input signal is VDDL (see state 104), the transistors N1 and P2 are activated and the transistor N2 is deactivated.
However, transistor P1 is partially activated or fully activated, depending on a value of VDDH, VDDL, and a device threshold voltage (Vth). In one example, VDDL=0.8V±10% VDDH=1V±10%, and Vth=200 mV-350 mV. In such case, a worst case involves a situation where VDDL=0.72V, VDDH=1.1V, and Vth=200 mV. For the transistor P1, the source voltage is 1.1V and the gate voltage is 0.72V, with the difference being 380 mV, which is larger than the threshold voltage 200 mV. Thus, in such situation, the transistor P1 is fully activated. Since the transistors P1 and N1 are fully activated, there is a DC current path 206 between VDDH and ground, which consumes a large amount of power.
FIG. 3 shows a buffer-type level shifter 300 adapted for avoiding a DC current flow when converting a signal from a VDDL domain to a VDDH domain, in accordance with the prior art. As shown, the level shifter 300 includes complimentary dual rail inputs IN and INB from the VDDL domain. When IN=VDDL and INB=0, transistors N2 and P1 are activated, contact point b=0, contact point a=VDDH, OUT=VDDH, and transistors N1 and P2 are deactivated. On the other hand, when IN=0 and INB=VDDL, the transistors N1 and P2 are activated, the transistors N2 and P1 are deactivated, contact point b=VDDH, contact point a=0, and OUT=0. By this design, no DC current flows through VDDH to ground.
However, such a design requires hundreds of signals from the VDDL domain to the VDDH domain. To this end, the dual rail inputs IN and INB require twice the number of signals to be routed. Unfortunately, such a design is thus cost-prohibitive.
FIG. 4 shows a single rail input level shifter 400 that addresses the problems with dual rail input level shifters (see, for example, FIG. 3), in accordance with the prior art. As shown, a single rail input is provided for increased power savings. More information regarding such single rail input level shifter 400 may be found with reference to a co-pending application filed Nov. 13, 2006 under application Ser. No. 11/559,155, which is incorporated herein by reference.
Unfortunately, none of the aforementioned level shifters accommodate situations where the VDDL domain is powered down for additional power savings purposes. Specifically, it often desired to power down the VDDL domain when its use is not required. To accomplish this power down, VDD may be cut off, such that any nodes internal to the VDDL domain are floating at an unknown value. As will be now set forth, some problems arise when attempting such VDDL domain power down.
FIG. 5 shows an inverter 500 that illustrates one problem with powering down a low voltage domain, in accordance with the prior art. During power down, the VDD is cut off, and all internal nodes float with an unknown value. If an input signal IN of the inverter 500 comes from a powered down block, the input signal IN may be any value. If IN=VDD/2, however, transistors P1 and N1 are activated, thus allowing a DC current 502 to flow through the transistors P1 and N1.
FIG. 6 shows a two input OR-gate 600 that addresses the problem with powering down a low voltage domain, in accordance with the prior art. As shown, a two input OR gate may be configured for power down control as well as avoiding DC current caused by floating input signals. An input signal IN is shown to be a floating input, and a power down signal PD is also provided. During a normal mode of operation, PD=0 and OUT=IN. In a power down mode, PD=VDD, and a PMOS transistor P2 is deactivated. Further, regardless as to what the input signal IN, OUT=VDD and there is no DC current flow.
To date, there is a continuing need to address such problems during a power down mode. For example, in the context of the level shifter 400 of FIG. 4, if a VDDL block is in the power down mode, VDDL_REF and an input signal IN can be any value between 0 and VDDL. Assume, in one example of operation, IN=VDDL/2 and VDDL_REF=VDDL. Since VDDH−Vthp>VDDL/2>Vthn, transistors P2, P3 and N2 are activated, and there is a DC current flowing through the transistors P2, P3 and N2. Further, contact point b is possibly around VDDH/2 and thus causes DC current flow through an associated output inverter.